Universitat Politècnica de Catalunya - UPC

Efficient BIST architecture to detect defects in TSVs

Posted by Universitat Politècnica de Catalunya - UPCResponsive · Patents for licensing · Spain

Summary of the technology

A new BIST (Built-in Self-Test) architecture has been developed to detect defects in TSVs (Through Silicon Vias) during the pre-bond phase. A simple circuit is included to detect defective TSVs affected by hard and/or weak defects, adding low area overhead and applying a simple and fast test methodology. The same circuit can be subsequently re-used for reconfiguration if a defective TSV has been detected. Partners to further develop the technology and/or to establish commercial agreements along with technical cooperation are sought.

Universitat Politècnica de Catalunya - UPC

The Challenge


Three-dimensional integrated circuits (3-D ICs) have arisen as a promising solution to attend the continuously increasing demands from the semiconductor industry. A 3-D IC integrates in a single package a vertical stack of tiers interconnected by means of Through Silicon Vias (TSVs). TSVs are critical elements susceptible to undergo defects during the manufacturing process. The detection of defective TSVs in the earliest process step is a key factor to prevent yield loss. Hence, specific testing of TSVs are done before every tier is stack, the so-called pre-bond test. However, pre-bond testing is still challenging. TSVs are too small for pre-bond test probe and present built-in self test (BIST) architectures suffer from some disadvantages, namely: lack for detection for weak defects, large area overhead and long test application times. In this context, new test approaches are required to efficiency detect defects in TSVs during the pre-bond test.

The Technology


The present invention allows to perform a fast and effective test of TSVs structures during the pre-bond phase by comparing the behavior between the TSV under test and a reference element. The invention takes into account that TSVs has only a terminal accessible during this stage of the manufacturing process. The reference element is a spare TSV included commonly for reconfiguration purposes. The same spare TSV can be used to test a set of TSVs, minimizing area overhead. The BIST architecture is a small and simple circuit so that it can subsequently re-used for reconfiguration purposes if a defective TSV is detected.

Current stage of development


Successful electrical simulations results have been obtained for different technology nodes, including process variations.

Applications and Target Market


The technology can be of especial interest to semiconductors manufacturers of 3-D ICs.

Innovative advantages


Detection of common hard and weak defects affecting TSVs.
Fast and simple test methodology.
Low area overhead.
Re-use of the architecture for subsequent reconfiguration, if required.

Intellectual property status

Granted Patent
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Technology available for licensing with technical cooperation Patent Status Priority application

Technology Owner

Universitat Politècnica de Catalunya - UPC

Technology Transfer Office

Related keywords

  • Electronics, IT and Telecomms
  • 3D printing
  • 3D printing design and modelling
  • Industrial manufacturing, Material and Transport Technologies
  • Semiconductors Technology
  • 3D
  • Customised semiconductors
  • Semiconductors Market

About Universitat Politècnica de Catalunya - UPC

Technology Transfer Office from Spain

The Universitat Politècnica de Catalunya - BarcelonaTech is a public institution dedicated to higher education and research in the fields of engineering, architecture and science, which contributes its knowledge and expertise in order to increase scientific output, transfer its results to society and provide a network of scientific and technical state-of-the-art facilities and technology valorization services that place us at the leading edge of innovation and economic development.

The UPC has established itself as a driver of innovation and is the technology partner of choice for companies and organizations with which it develops projects and builds partnerships. A role borne out by the numerous agreements and research projects that have been set in motion by groups, organizations and laboratories; the creation of new technology-based companies; the generation and exploitation of patents, and the scientific and technical services UPC makes available to its environment in order to generate progress and employment.

The Technology Transfer Office (SGI) is responsible of Designing, coordinating and implementing research valorisation strategies, carrying out the protection policy of the research results, marketing these results through license contracts and designing and setting up the University's enterprise creation model in order to transfer the results of the research to the market, protect and commercialize these results, promote the culture of entrepreneurship and innovation, and create technology-based companies within the UPC environment.

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