Wafer scale technique for interconnecting vertically stacked dies

BACKGROUND

While the integration of more transistors on a single piece of silicon has continued almost undisturbed for the past 40 years, recent generations of processors are beginning to suffer from a growing shortage of bandwidth for CPU to memory bandwidth. One attempted solution is in the form of 3D stacking of multiple silicon dies in an effort to offer some relief in terms of co -integration of memory and processing capabilities. For implementation in silicon, thinner dies and through silicon vias (TSVs) have been developed as an interconnect solution between different stacked dies. While stacked chip may indeed solve some of the bandwidth issue, it raises concerns about heat dissipation and thermal management. Recently the use of micro-fluidics channel, etched through the bottom of the stacked dies, to pump chilled water through capillaries between the sandwiched silicon layers has been demonstrated as a solution to the heat dissipation problem, but this requires thicker dies and makes the use of Through Silicon Via' s (TSV) for interconnecting the layers complicated. Interconnect density is becoming a serious problem in high end processors. Three-dimensional (3D) device stacking is a promising approach to increase density and scalability. Turning now to application in the field of interconnects and co -integration of electronics and photonics, a critical issue affecting the performance of state of the art silicon processors is the limited interconnect density. A possible solution to this problem may be found in the form of optical interconnect channels. Compared with metal wires, optical interconnect links exhibit inherent advantages for transferring signals from one place to another. Owing to photons lack of electrical charge, transmission loss is small and independent of data rate. Optics can certainly avoid density limitations encountered in electrical systems, if the whole top surface of the chip can be used for placing vertically emitting lasers and photo detectors for data communication, as the area scales quadratically with the chip's size allowing for an estimated 50 Tb/s for a chip measuring 310 mm<2>. The question is how to integrate the opto-electrical components with the electronic driving circuits in the most advantageous way.  

Closely stacking opto-electrical dies onto the top surface of a CMOS chip can maximize high speed interconnect performance and reduce the device footprint. Among all the stacking technologies, TSV is the most efficient 3D stacking approach, but it can only be used for thin silicon die stacks. 850nm opto-electrical dies widely used in the optical interconnect are based on GaAs, neither GaAs substrate nor silicon CMOS substrate are transparent at 850nm. An optical transceiver with physically drilled holes through CMOS for light path after flip chip attachment has been developed. However, to realize holes in this special CMOS IC, approximately 20 RIE steps were required to etch through the film stack to expose the silicon wafer. Another demonstration is using wire bonding to connect opto-electrical device and CMOS. The opto-electrical die was thinned down to 25 μιη before integration, which makes the opto-electrical device very fragile. In addition wire bonds introduce stray inductances which limit eventual bandwidth of interconnects. What is needed is a process that integrates the opto-electrical components with the electronic driving circuits in the most advantageous way that allows for 3D stacking of multiple dies on top of each other regardless of their composition in a cost effective and wafer scalable method.

SUMMARY OF THE INVENTION

A method of interconnecting stacked die surfaces with electrically conductive traces is provided that includes bonding, using a first layer of a photoresist compound, spun on top of the bottom die and placing a second die on top of the first die. The photoresist acts as the bonding agent and can be controlled for thickness by controlling the photoresist deposition speed and amounts. The assembled device can then be exposed to UV light, which will cause all the resist on top of the bottom die, which is not covered by the second die, to be removed in the development stage. Heating the remaining photoresist sitting between the dies above a pyrolyzation point of the photoresist compound, will cause the photoreisst compound to transitions to a stable layer. Sufficient photoresist is then deposited on the stacked dies to allow for coverage of bottom and top dies. This layer of photoresist is then exposed to UV light with an appropriate mask and developed to leave areas of photoresist overlapping the pads to be connected on top and bottom surfaces. Heating the photoresist compound areas causes the photoresist to return to its liquid state, which in turn results in the fomiing of a smooth convex bridge between the first die top surface and the second die top surface. Finally a seeding layer is deposited on top of the whole sub assembly, and a photoresist layer is used to define areas for electro-plating the required electrically conductive traces on the smooth convex bridge, forming the interconnect layer between the first die top surface and the second die top surface.

Desired business relationship

Patent licensing